1. Field of the Invention
This invention relates to a memory array and peripheral circuits and methods for writeable memory technologies.
More particularly this invention relates to providing a memory array and peripheral circuits which allow byte access for programming, erasing and reading.
In addition, this invention relates to the ability of providing enhanced long-term reliability for memory arrays by reducing the cumulative voltage stressing of writeable memory arrays.
2. Description of Related Art
Memory cells which can be programmed and erased and re-programmed are known as Electrically, Erasable Programmable Read Only Memory, EEPROM. In the prior art, there are known types of memory arrays and peripheral circuits which are used with EEPROM, flash memory, or non-volatile memory. The main deficiencies of the prior art are the inability to access the memory arrays on a byte basis for programming, erasing and reading the memory arrays. Another deficiency of the prior art is the large amount of voltage stress required to program and erase the memory cells of the array.
U.S. Pat. No. 5,812,452 (Hoang) “Electrically Byte-Selectable and Byte-Alterable Memory Arrays” describes a memory array which utilizes a byte (block) select transistor to allow the memory cells to be accessed and altered on a byte basis.
U.S. Pat. No. 6,201,732 B1 (Caywood) “Low Voltage Single CMOS Electrically Erasable Read-Only Memory” describes a CMOS memory cell which can can be programmed, erased and operate at low voltages.
U.S. Pat. No. 6,128,220 (Banyai et al.) “Apparatus for Enabling EEPROM Functionality Using a Flash Memory Device” discloses a byte-alterable non-volatile memory.
U.S. Pat. No. 6,088,269 (Lambertson) “Compact Page-Erasable EEPROM Non-Volatile Memory” discloses a page erasable memory which uses two layers of conductive or semiconductive material.